Preliminary Specifications: Programmed Data Processor Model Three (PDP-3) October, 1960 - Digital Equipment Corporation (top 100 novels .TXT) 📗
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The PDP-3 is a "fixed" point machine using binary arithmetic. Negative numbers are represented as the 1's complement of the positive numbers. Bit 0 is the sign bit which is ZERO for positive numbers. Bits 1 to 35 are magnitude bits with bit 1 being the most significant and bit 35 being the least significant.
The actual position of the binary point may be arbitrarily assigned to best suit the problem in hand. Two common conventions in the placement of the binary point are:
The binary point is to the right of the least significant digit, thus, numbers represent integers. The binary point is to the right of the sign digit, thus the numbers represent a fraction which lies between ±1.The conversion of decimal numbers into the binary system for use by the machine may be performed automatically by subroutines. Similarly the output conversion of binary numbers into decimals is done by subroutine. Operations for floating point numbers are handled by programming. The utility program system provides for automatic insertion of the routines required to perform floating point operations and number base conversion (see Utility Programs).
INDEXINGIn PDP-3, 511 registers of the main magnetic core memory are available for use as automatic index registers. Their addresses are specified by octal digits 3 to 5 of the instruction word. These registers are memory locations 001-777 (octal). Address 000 specifies that no index register is to be used with the instructions. The contents of octal digits 7 through 11 of the selected index register are added to the unmodified address (octal digits 7 through 11 of the instruction).
This sum is used to locate the operand. The addition is done in the Index Adder which is a 15 bit 1's complement adder. The contents of the Accumulator and the In-Out Register are unaffected by the indexing process. An instruction which has used indexing is retained in memory with its original address unmodified. Memory registers 1-777 (octal) are available for use as normal memory registers if they are not being used as index registers. The left half of these registers is available for the storage of constants, tables, etc., when octal digits 7 through 11 act as index registers.
Three special instructions snx, spx and lir, are available to facilitate resetting, advancing, and sampling of the index registers. Since the index registers are normal memory registers, their contents can also be manipulated by the standard computer instructions.
INDIRECT ADDRESSINGAn instruction which is to use an indirect address will have a ONE in bit six of the instruction word. The original address, Y, of the instruction will not be used to locate the operand of the instruction, as is the normal case. Instead, it is used to locate a memory register whose contents in octal digits 7 through 11 will be used as the address of the original instruction. This new address is known as the indirect address for the instruction and will be used to locate the operand. If the memory register containing the indirect address also has a 1 in bit six, the indirect addressing procedure is repeated again and a third address is located. There is no limit to the number of times this process can be repeated.
Index registers may be used in conjunction with indirect addressing. In this case, the address after being modified by the selected index register is used to locate the indirect address.
The indirect address can be acted on by an index register and deferred again if desired. Each use of an index register or an indirect address extends the operating time of the original instruction by 5 microseconds.
INSTRUCTION LISTThis list includes the title of the instruction, the normal execution time of the instruction, i.e., the time with no indexing and no deferring, the mnemonic code of the instruction, and the operation code number. The notation used requires the following definitions. The contents of a register Q are indicated as C(Q). The address portion of the instruction is indicated by Y. The index register address of an instruction is indicated by x. The effective address of an operand is indicated by Z. Z may be equal to Y or it may be Y as modified by deferring or by indexing.
Indexable Memory Instructions Arithmetic InstructionsAdd(10 usec.)
add x Y Operation Code 40
The new C(AC) are the sum of C(Z) and the original C(AC). The C(Z) are unchanged. The addition is performed with 1's complement arithmetic.
If the sum exceeds the capacity of the Accumulator Register, the overflow flip-flop will be set (see Skip Group instructions).
Subtract(10 usec.)
sub x Y Operation Code 42
The new C(AC) are the original C(AC) minus the C(Z). The C(Z) are unchanged. The subtraction is performed using 1's complement arithmetic.
If the difference exceeds the capacity of the Accumulator, the overflow flip-flop will be set (see Skip Group instructions).
Multiply(approximately 25 usec.)
mul x Y Operation Code 54
The C(AC) are multiplied by the C(Z). The most significant digits of the product are left in the Accumulator and the least significant digits in the In-Out Register. The previous C(AC) are lost.
Divide(approximately 90 usec.)
div x Y Operation Code 56
The Accumulator and the In-Out Register together form a 70 bit dividend. The high order part of the dividend is in the Accumulator. The low order part of the dividend is in the In-Out Register. The divisor is (Z).
Upon completion of the division, the quotient is in the In-Out Register. The remainder is in the Accumulator. The sign of the remainder is the same as the sign of the dividend. If the dividend is larger than C(Z), the overflow flip-flop will be set and the division will not take place.
Logical InstructionsLogical AND(10 usec.)
and x Y Operation Code 02
The bits of C(Z) operate on the corresponding bits of the Accumulator to form the logical AND. The result is left in the Accumulator. The C(Z) are unaffected by this instruction.
Logical AND Function Table
AC Bit C(Z) Bit Result 0 0 0 0 1 0 1 0 0 1 1 1Exclusive OR(10 usec.)
xor x Y Operation Code 06
The bits of C(Z) operate on the corresponding bits of the Accumulator to form the exclusive OR. The result is left in the Accumulator. The C(Z) are unaffected by this order.
Exclusive OR Table
AC Bit C(Z) Bit Result 0 0 0 0 1 1 1 0 1 1 1 0Inclusive OR(10 usec.)
ior x Y Operation Code 04
The bits of C(Z) operate on the corresponding bits of the Accumulator to form the inclusive OR. The result is left in the Accumulator. The C(Z) are unaffected by this order.
Inclusive OR Table
AC Bit C(Z) Bit Result 0 0 0 0 1 1 1 0 1 1 1 1 General InstructionsLoad Accumulator(10 usec.)
lac x Y Operation Code 20
The C(Z) are placed in the Accumulator. The C(Z) are unchanged. The original C(Z) are lost.
Deposit Accumulator(10 usec.)
dac x Y Operation Code 24
The C(AC) replace the C(Z) in the memory. The C(AC) are left unchanged by this instruction. The original C(Z) are lost.
Deposit Address Part(10 usec.)
dap x Y Operation Code 26
Octal digits 6 through 11 of the Accumulator replace the corresponding digits of memory register Z.
C(AC) are unchanged as are the contents of octal digits 0 through 5 of Z. The original contents of octal digits 6 through 11 of Z are lost.
Deposit Instruction Part(10 usec.)
dip x Y Operation Code 30
Octal digits 0 through 5 of the Accumulator replace the corresponding digits of memory register Z. The Accumulator is unchanged as are digits 6 through 11 of Z. The original contents of octal digits 0 through 5 of Z are lost.
Load In-Out Register(10 usec.)
lio x Y Operation Code 22
The C(Z) are placed in the In-Out Register. C(Z) are unchanged. The original C(IO) are lost.
Deposit In-Out Register(10 usec.)
dio x Y Operation Code 32
The C(IO) replace the C(Z) in memory. The C(IO) are unaffected by this instruction. The original C(Z) are lost.
Jump(5 usec.)
jmp x Y Operation Code 60
The Program Counter is reset to address Z. The next instruction that will be executed will be taken from memory register Z. The original contents of the Program Counter are lost.
Jump and Save Program Counter(5 usec.)
jsp x Y Operation Code 62
The contents of the Program Counter are transferred to the Index Adder. When the transfer takes place, the Program Counter holds the address of the instruction following the jsp. The Program Counter is then reset to address Z. The next instruction that will be executed will be taken from memory register Z.
Skip if Accumulator and Z differ(10 usec.)
sad x Y Operation Code 50
The C(Z) are compared with the C(AC). If the two numbers are different, the Program Counter is indexed one extra position and the next instruction in the sequence is skipped. The C(AC) and the C(Z) are unaffected by this operation.
Skip if Accumulator and Z are the same(10 usec.)
sas x Y Operation Code 52
The C(Z) are compared with C(AC). If the two numbers are identical, the Program Counter is indexed one extra position and the next instruction in the sequence is skipped. The C(AC) and C(Z) are unaffected by this operation.
Non-Indexable Memory InstructionsThese instructions have the same word format as the indexable instructions. Since they operate on the index register location, x, they cannot be indexed.
Skip on Negative index(10 usec.)
snx x Y Operation Code 46
The number in octal digits 7 through 11 of the instruction word is added to the C(x). This addition is done in the 15 bit Index Adder using 1's complement arithmetic. If, after the addition, the sum is negative, the Program Counter is advanced one extra position and the next instruction in the sequence is skipped. The contents of octal digits 0-5 of the index register location are unaffected by this instruction.
Skip on Positive index(10 usec.)
spx x Y Operation Code 44
The number in octal digits 7 through 11 of the instruction word is added to the C(x). This addition is done in the 15 bit Index Adder using 1's complement arithmetic.
If, after the addition, the sum is positive, the Program Counter is advanced one extra position and the next instruction in the sequence is skipped. The contents of octal digits 0-5 of the index register location are unaffected by this instruction.
Load Index Register(10 usec.)
lir x Y Operation Code 14
The octal digits 7 through 11 (Y) of the instruction will replace the corresponding digits of the memory register specified by x. Octal digit 6 of the memory register will be left clear. Digits 0-5 of the memory register are unchanged.
Deposit Index Adder(10 usec.)
dia x Y Operation Code 16
The C(IA) replace the octal digits 7 through 11 of memory location Y. Octal digit 6 of Y is cleared. Digits 0 through 5 of Y are left unchanged. The x portion of the instruction is ignored.
Non-Memory Instructions Rotate and Shift GroupThis group of instructions will rotate or shift the Accumulator and/or the In-Out Register. When the two registers operate combined, the In-Out Register is considered to be a 36 bit magnitude extension of the right end of the Accumulator.
Rotate is a non-arithmetic cyclic shift. That is, the two ends of the register are logically tied together and information is rotated as
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